1. Field of the Invention
This invention relates generally to a timer counter unit utilized in computer systems and, more particularly, to a method of pipelining the servicing of the multiple timers in the timer counter unit.
2. Discussion of the Related Art
The timer counter unit in a computer system can serve various functions. Some of these functions include being used as a real-time clock, a square-wave generator and a digital one-shot. These and other functions can be implemented in a system design. For example, a real-time clock can be used to provide a system clock tick for peripheral devices.
Referring to FIG. 1 there is shown a timer counter unit 100 which is composed of three independent timers, timer 0 and associated timer 0 registers 102, timer 1 and associated timer 1 registers 104, and timer 2 and associated timer 2 registers 106, (the associated registers will be discussed later) CPU 108, and a counter element 110. The timer counter unit can thus be modeled as a single counter element, time multiplexed to three register banks. Each timer operates independently of the CPU 108. The individual timers in the timer counter unit 100 are serviced over 4 clock periods, one timer during each clock with an idle clock at the end of the servicing period (see FIG. 4). The step of servicing a timer consists of two functions; (1) processing the control bits of the timer's associated control register to determine the necessary actions and (2) implementing the necessary actions of incrementing the count element and making comparisons with the timer's associated maxcount register values. The prior art systems execute both of the two functions in the same clock period. However, as CPU clocks have been required to be faster and faster, the time for servicing the timer has become concomitantly smaller and smaller. To provide a solution to the required faster CPU clocks, it would require the present timer architecture to either use more clocks to service the timer counter or to speed up the counting block. However, these solutions are deleterious to the performance of the timer counter unit and the computer system and require the system designer to reserve more chip space for the timer counter unit.
One method to avoid the problems associated with the above two solutions is to develop a pipelining architecture for the timer control logic. The pipelining of the timer control logic would provide that the two functions of the timer service are done in a pipeline method, each of the functions utilizing a clock, one after the other. Since this would be done in a pipeline, the total number of clocks to service the three timers would still be the same as the prior art devices. Because the total timer service would be split into two functions, the time required for each function would be less, therefore each function would be accomplished in a faster CPU clock. This would provide that the timer counter logic does not have to speed up. The pipelining architecture would provide that the three timers share the same control logic and counting block. In the prior art, in each timer service clock the control register bits of that timer are loaded into the control logic and are then processed to determine if any service is required for that timer. The service is then executed in the remaining part of that same clock.
What is needed is a pipelining architecture that would have the first part of the servicing routine done in one clock and the second part of the servicing routine done in the following clock in which each servicing routine takes less per clock time than both functions of the control service per timer in the prior art.